This invention is related to a high-breakdown voltage heterostructure field-effect transistor with high temperature operation ability.
In general, attributed to harsh thermal environment, transistors operation suffer from some disadvantages such as (1) the increase of gate leakage current, (2) the reduction of effective gate Schottky barrier, (3) the reduction of breakdown voltage, (4) the increase of threshold voltage, and (5) the decrease of transconductance, etc. Further, the device scale of IC and the space between electrodes are expected to gradually decrease. Consequently, the fields between gates and drains of field effect transistors and between base and collector of the bipolar transistors could bring about breakdown thereof.
Recently, due to the improvements of semiconductor technique and the development of new microwave materials, many methods and structures have been proposed by researchers to enhance the breakdown voltage of FET devices, and several of them have been successfully utilized for space exploration, satellite, automatic control system, navigation, radar, and subterranean exploration applications. Among them, devices fabricated with (1) SiC, (2) GaN, (3) AlAs, (4) AlGaAs, and (5) diamond show excellent high-temperature and high-breakdown characteristics. It is clear that there is still a great need in the semiconductor industry to develop a device having high-breakdown voltage and high-temperature endurable ability.
The present invention provides a high-breakdown voltage heterostructure field-effect transistor for high temperature operations. More particularly, the present invention provides a high-breakdown voltage heterostructure field-effect transistor comprising a GaInP/GaAs structure for high temperature operations.
A high-breakdown voltage heterostructure field-effect transistor constructed according to the present invention comprises:
a semiconductor substrate;
an undoped buffer layer formed on said substrate;
a delta-doped sheet formed on said undoped buffer layer;
an undoped layer formed on said delta-doped sheet;
a sub-channel layer formed on said undoped layer;
an active channel layer formed on said sub-channel layer;
a gate layer formed on said active channel layer; and
an ohmic contact layer formed on said gate layer, wherein said gate layer and said ohmic contact layer are so formed such that said active channel layer has exposed portions.
Preferably, said delta-doped sheet has a doping concentration ranging from 2xc3x971012 to 1xc3x971013 cmxe2x88x923.
Preferably, said substrate of the transistor of the present invention is a semi-insulating GaAs; said undoped buffer layer is an undoped GaAs having a thickness of 0.1-2.0 xcexcm; said undoped layer formed on said delta-doped sheet is GaAs having a thickness of 50-100 xc3x85; said sub-channel layer is InxGa1xe2x88x92xAs having a thickness of 100-200 xc3x85, where x=0.05-0.25; said active channel layer is n-type GaAs having a thickness of 1500-3000 xc3x85 and an n-type dopant concentration of n=1xc3x971017-5xc3x971017 cmxe2x88x923; said ohmic contact layer is an n-type GaAs having a thickness of 200-3000 xc3x85 and an n-type dopant concentration of n=1xc3x971018-1xc3x971019cmxe2x88x923; and said gate layer is p-type Ga0.51In0.49P having a thickness of 80-120 xc3x85 and a p-type dopant concentration of p=6xc3x971018-1xc3x971019cmxe2x88x923, p-type AlxGa1xe2x88x92xAs having a thickness of 80-120 xc3x85 and a p-type dopant concentration of p=6xc3x971018-1xc3x971019 cmxe2x88x923, where x=0.2-0.5, or Al0.5In0.5P having a thickness of 80-120 xc3x85 and a p-type dopant concentration of p=6xc3x971018-1xc3x9719 cmxe2x88x923.
Preferably, said transistor of the present invention further comprises a gate electrode which forms an ohmic contact with said ohmic contact layer, and more preferably said gate electrode is Au.
Preferably, said transistor of the present invention further comprises a drain electrode and a source electrode on said exposed portions of said active channel layer, each of which forms an ohmic contact with said active channel layer, and more preferably said drain electrode and said source electrode are Au/Ga/Ni metal.
Alternatively, said substrate of said transistor of the present invention is a semi-insulating InP; said undoped buffer layer is InP having a thickness of 0.1-2.0 xcexcm; said undoped layer formed on said delta-doped sheet is InP having a thickness of 50-100 xc3x85; said sub-channel layer is InxGa1xe2x88x92xAs having a thickness of 100-200 xc3x85, where x=0.45-0.6; said active channel layer is n-type InxGa1xe2x88x92xAs having a thickness of 1500-3000 xc3x85 and an n-type dopant concentration of n=1xc3x971017-5xc3x971017 cmxe2x88x923; said gate layer is p-type Al0.48In0.52As having a thickness of 80-120 xc3x85 and a p-type dopant concentration of p=6xc3x971018-1xc3x971019 cmxe2x88x923; said ohmic contact layer is n-type InxGa1xe2x88x92xAs having a thickness of 200-3000 xc3x85 where x=0.45xcx9c0.6 and an n-type dopant concentration of n=1xc3x971018-1xc3x971019 cmxe2x88x923.
The structure of a device fabricated in accordance with one of the preferred embodiments of the present invention has the following features:
(1) A high barrier gate structure is formed with n+-GaAs/p+-Ga0.51In0.49P/n-GaAs heterojunction. It might be attributed to the existence of conduction band discontinuity value (xcex94Ec) of about 200 meV and valance band discontinuity value (xcex94Ev) of about 300 meV at Ga0.51In0.49P/GaAs heterojunction, electrons are confined within the channel layers, and thus excellent characteristics such as high transconductance, low leakage current, and high breakdown voltage are obtained;
(2) Due to the existence of GaAs/In0.15Ga0.85As/GaAs heterojunction, a conduction band of said sub-channel layer made of In0.15Ga0.85As epitaxial layer will form a quantum-well structure, so that the confinement effect of electrons and the linearity performance of the device are enhanced,
(3) Further, an inverted delta-doped sheet is used to act as a carrier supplier to said sub-channel layer, so that the electron concentration and mobility can be enhanced, and the impurity scattering effect can be reduced.
When the structure of the present invention is adopted to fabricate a device, not only can improve the performance of the device, but also can enhance the high-temperature characteristics thereof. In view of above, the structure of the present invention is applicable to the fabrication of a field-effect transistor. Moreover, it has a great potential in the application of high-frequency microwave communication circuits, and in particular, the structure provides a promise for space exploration, satellite technology, automatic control system, navigation, radar, and the subterranean exploration applications.